EE/CS 120A: Logic Design | Winter 2005 |
Subject area: EE/CS | Course number: 120A | Section number: 001 | |
Course title: LOGIC DESIGN | Units: 5 | ||
Call number: 13075/12279 | Instructor(s): Fonoberov V | ||
Class type: LEC | Day: TR | Time: 6:40pm-8pm | Location: BRNHL A125 |
Final exam: 03/17/2005 7 to 10 p.m. | Max enrollment: 90 Seats Available: 42 |
Status: Open | |
Activity Control: REGISTRATION REQUIRED FOR LEC, LAB | |||
Prerequisite(s): CS 061 with a grade of "C-" or better | |||
UCR General Catalog 2004-2005:
EE/CS 120A. Logic Design 5 Lecture, 3 hours; laboratory, 6 hours. Prerequisite(s): CS 061 with a grade of "C-" or better. Covers the design of digital systems. Topics include Boolean algebra; combinational and sequential logic design; design and use of arithmetic-logic units, carry-lookahead adders, multiplexors, decoders, comparators, multipliers, flip-flops, registers, and simple memories; state-machine design; and basic register-transfer level design. Laboratories involve use of hardware description languages, synthesis tools, programmable logic, and significant hardware prototyping. |
Lecture:
Section 001: TR 6:40pm-8pm, BRNHL A125.
Instructor: Dr. Vladimir Fonoberov
(vladimir@ee.ucr.edu).
Office hours: Wed 2:00pm-3:00pm, BRNHL B235B.
Labs:
Section 021: MF 4:10pm-7pm, BRNHL B252.
Teaching Assistant: Jiangang Yu (jyu@ee.ucr.edu).
Office hours: Wed 2:00pm-4:00pm, BRNHL B252.
Section 022: TR 8:10am-11am, BRNHL B252.
Teaching Assistant: Zhao Zhuo (zhaozhuo@ee.ucr.edu).
Office hours: Wed 2:00pm-4:00pm, BRNHL B252.
Section 023: WF 8:10am-11am, BRNHL B252.
Teaching Assistant: Xiaojun Tang (xtang@ee.ucr.edu).
Office hours: Wed 2:00pm-4:00pm, BRNHL B252.
Course Objectives:
The ABET course objectives can be found here.
Textbooks:
"Digital Design" by Frank Vahid (main textbook).
"Logic and Computer
Design Fundamentals" by M. Morris Mano and Charles R. Kime, 3rd or 2nd Edition.
Course grading:
The course consists of 100 points:
Grades will be assigned using a conventional grading scale: 100-90 A, 89-80 B, 79-70 C, 69-60 D, 59-0 F (+/- grades will be given).
(subject to change as the quarter progresses)
Homework 1: 1.5, 1.8, 1.15, 1.18, 2.11, 2.13, 2.18, 2.24, 2.28, 2.29 (due on Jan. 13) [download: DOC or PDF].
Quiz 1.
Quiz 2.
MIDTERM.
Quiz 3.
Quiz 4.
Review.
(subject to change as the quarter progresses)
Read the lab overview and report format.
Xilinx schematic entry and simulation: Appendix A
Xilinx download to development board: Appendix B
Xilinx VHDL entry: Appendix C
Last modified: February 23, 2005; 03:39 PM