EE/CS 120A: Logic Design

EE/CS 120A: Logic Design

Summer 2005

Webpage for previous course offering (Winter 2005)

Subject area: EE/CS	Course number: 120A	Section number: 101
Course title: LOGIC DESIGN		Units: 5
Call number: 10563/10389		Instructor(s): Fonoberov V
Class type: LEC	Day: MTWTh	Time: 8:00-9:30am	Location: Sproul Hall 2355
Final exam: Fri. 7/22/2005 8:00-10:00am		Max enrollment: 50 Seats Available: 18	Status: Open
Activity Control: REGISTRATION REQUIRED FOR LEC, LAB
Prerequisite(s): CS 061 with a grade of "C-" or better
UCR General Catalog 2004-2005: EE/CS 120A. Logic Design 5 Lecture, 6 hours; laboratory, 12 hours. Prerequisite(s): CS 061 with a grade of "C-" or better. Covers the design of digital systems. Topics include Boolean algebra; combinational and sequential logic design; design and use of arithmetic-logic units, carry-lookahead adders, multiplexors, decoders, comparators, multipliers, flip-flops, registers, and simple memories; state-machine design; and basic register-transfer level design. Laboratories involve use of hardware description languages, synthesis tools, programmable logic, and significant hardware prototyping.

Basic Information

Lecture:
Section 101: MTWTh 8:00 - 9:30 a.m., Sproul Hall 2355
Instructor: Dr. Vladimir Fonoberov (vladimir.fonoberov@ucr.edu)
Office hours: Wed 2:00 - 3:00 p.m., Bourns Hall B235B
Labs:
Section 121: MTWTh 10:00 a.m. - 1:00 p.m., Bourns Hall B156
Teaching Assistant: Rong Wang (rwang@ee.ucr.edu)
Office hours: to be announced, Bourns Hall B156

Section 122: MTWTh 3:00 - 6:00 p.m., Bourns Hall B156
Teaching Assistant: Zhuo Zhao (zhaozhuo@ee.ucr.edu)
Office hours: to be announced, Bourns Hall B156
Text:
"Digital Design" by Frank Vahid (ISBN 0-471-70831-3)
Course grading:
The course consists of 100 points:
- Lecture component (70 points)
  - 30 pts: Final
  - 20 pts: Midterm
  - 10 pts: Quizzes (4 @ 2.5 pts)
  - 10 pts: Homework (4 @ 2.5 pts)
- Lab component (30 points)
  - 27 pts: Lab assignments (9 @ 3 pts)
  - 3 pts: Lab practical exam
Grades will be assigned as follows: 100-90 A, 89-80 B, 79-70 C, 69-60 D, 59-0 F (+/- grades will be given).

(subject to change as the quarter progresses)

Week 1: June 20-23
- Combinatorial Logic Design
- Homework 1: 1.5, 1.8, 1.15, 1.18, 2.11, 2.13, 2.18, 2.24, 2.28, 2.29 (due on June 23) [download: DOC or PDF]
- Quiz 1 (June 23)
Week 2: June 27-30
- Sequential Logic Design - Controllers
- Homework 2: 6.3, 6.4, 2.36, 2.38, 2.44, 2.47, 2.57, 3.6, 3.8, 3.10 (due on June 30) [download: DOC or PDF]
- Quiz 2 (June 30)
Week 3: July 5-7
- Review (July 5)
- MIDTERM (July 6)
- Datapath Components
Week 4: July 11-14
- Register-Transfer Level (RTL) Design
- Homework 3: 4.2, 4.3, 4.10, 4.11, 4.17, 4.34, 4.35, 4.45, 4.47, 4.51 (due on July 14) [download: DOC or PDF]
- Quiz 3 (July 14)
Week 5: July 18-21
- Physical Implementation
- Homework 4: 7.8, 7.9, 7.10 (due on July 20) [download: DOC or PDF]
- Quiz 4 (July 20)
- Review (July 21)
July 22, 2005: 8:00 - 10:00 a.m.
- FINAL EXAM

(subject to change as the quarter progresses)

Xilinx schematic entry and simulation: Appendix A
Xilinx download to development board: Appendix B
Xilinx VHDL entry: Appendix C

Material covered: You'll be responsible for learning material covered in lecture, in the textbook, and in lab. We expect you to read the textbook; lecture only emphasizes key material, but does not cover all required material alone.
Communicating with the instructor and TA: when sending electronic mail to the instructor or TA, please remember that many students have the same name, and your instructor may be teaching other courses too. So please give your full name and list the course you are referring to, and preferably include your student ID number. We prefer that you use your UCR email account so that you get used to it (remember that UCR sends many official notices now only by email). Please try to be polite and professional, and use reasonable grammar and formatting.
Re-grade policy: re-grade requests must be submitted in writing and within one week of the distribution of the graded material. Grade-database errors should also be pointed out within one week of posting.
Final grades: Per university policy, changes to your final grade will be made only in the event of a clerical error. Asking your instructor how far you were from a cutoff and what extra work you can do to improve the grade is not appropriate.

Last modified: June 20, 2005; 05:02 PM