EE/CS 120A: Logic Design

EE/CS 120A: Logic Design

Winter 2006

Webpages for previous course offerings (Winter 2005, Summer 2005)

Subject area: EE/CS	Course number: 120A	Section number: 001
Course title: LOGIC DESIGN		Units: 5
Call number: 13203/12390		Instructor(s): Fonoberov V
Class type: LEC	Day: TR	Time: 6:40 - 8:00 p.m.	Location: SPTHW 1307
Final exam: 03/23/2006 7-10 p.m.		Max enrollment: 46 Seats Available: 0	Status: Closed
Activity Control: REGISTRATION REQUIRED FOR LEC, LAB
Prerequisite(s): CS 061 with a grade of "C-" or better
UCR General Catalog 2005-2006: EE/CS 120A. Logic Design 5 Lecture, 3 hours; laboratory, 6 hours. Prerequisite(s): CS 061 with a grade of "C-" or better. Covers the design of digital systems. Topics include Boolean algebra; combinational and sequential logic design; design and use of arithmetic-logic units, carry-lookahead adders, multiplexors, decoders, comparators, multipliers, flip-flops, registers, and simple memories; state-machine design; and basic register-transfer level design. Laboratories involve use of hardware description languages, synthesis tools, programmable logic, and significant hardware prototyping.

Basic Information

Lecture:
Section 001: TR 6:40 - 8:00 p.m., SPTHW 1307
Instructor: Dr. Vladimir Fonoberov (vladimir.fonoberov@ucr.edu)
Office hours: Tuesday 2:00 - 4:00 p.m., ENGR2 222
Labs:
Section 021: MW 5:10 - 8:00 p.m., ENGR2 125
Teaching Assistant: Zhuo Zhao (zhaozhuo@ee.ucr.edu)
Office hours: to be announced, ENGR2 125

Section 022: TR 8:10 - 11:00 a.m., ENGR2 125
Teaching Assistant: Rui Li (ruili@ee.ucr.edu)
Office hours: to be announced, ENGR2 125
Text:
"Digital Design (Preview Edition)" by Frank Vahid, John Wiley & Sons, Inc., 2006 (ISBN 0-471-46784-7)
Course grading:
The course consists of 100 points:
- Lecture component (70 points)
  - 30 pts: Final
  - 20 pts: Midterm
  - 10 pts: Quizzes (4 @ 2.5 pts)
  - 10 pts: Homework (4 @ 2.5 pts)
- Lab component (30 points)
  - 27 pts: Lab assignments (9 @ 3 pts)
  - 3 pts: Lab practical exam
Grades will be assigned as follows: 100-90 A, 89-80 B, 79-70 C, 69-60 D, 59-0 F (+/- grades will be given).

Material covered: You should read the textbook. Lecture only emphasizes key material, but does not cover all required material.
Communicating with the instructor and TA: You must use your UCR e-mail account. E-mails sent from other accounts (Yahoo, Hotmail, MSN, AOL, GMail, etc.) will be treated as spam and deleted automatically.
Re-grade policy: Grade-database errors should be pointed out within one week of posting.
Final grades: Per university policy, changes to your final grade will be made only in the event of a clerical error.

(subject to change as the quarter progresses)

Week 1: January 10, 12
- Slides: Tuesday, Thursday
- HW #1 (due 01/19): 1.11, 1.22, 2.17, 2.27, 2.32, 2.34, 2.38, 2.39, 2.49, 2.58
Week 2: January 17, 19
- Slides: Tuesday
- Quiz #1 (01/19)
Week 3: January 24, 26
- Slides: Tuesday, Thursday
- HW #2 (due 02/02): 3.2, 3.4, 3.12, 3.13, 3.15, 3.22, 3.23, 3.24, 3.39, 3.40
Week 4: January 31, February 2
- Slides: Tuesday
- Quiz #2 (02/02)
Week 5: February 7, 9
- Review
- Midterm (02/09)
Week 6: February 14, 16
- Slides: Tuesday, Thursday
- HW #3 (due 02/23): 4.2, 4.3, 4.12, 4.18, 4.30, 4.32, 4.41, 4.44, 4.48, 4.52
Week 7: February 21, 23
- Slides: Tuesday
- Quiz #3 (02/23)
Week 8: February 28, March 2
- Slides: Tuesday, Thursday
- HW #4 (due 03/14): 6.3, 6.4, 5.2, 5.17, 5.36, 5.37, 7.10, 7.20, 7.23, 7.26
Week 9: March 7, 9
- Slides: Tuesday
- Slides: Thursday
Week 10: March 14, 16
- Quiz #4 (03/14)
- Review

(subject to change as the quarter progresses)

Xilinx schematic entry and simulation: Appendix A
Xilinx download to development board: Appendix B
Xilinx VHDL entry: Appendix C

Last modified: March 02, 2006; 04:59 PM